The present invention relates to the field of computer systems. More specifically, the present invention relates to a method and apparatus for trapping accesses to input/output (I/O) addresses.
In computer systems, processors typically communicate with I/O functions using memory-mapped I/O or I/O addressing. An I/O function is a specific job that an I/O device performs. An I/O device may host a plurality of I/O functions. The memory-mapped I/O scheme involves assigning portions of the memory to I/O functions as address spaces. Reads and writes to those addresses in memory are interpreted as commands to the I/O function. The I/O addressing scheme involves utilizing dedicated I/O instructions in the processor. These I/O instructions can specify an I/O function, through an I/O address, and a command to the I/O function. The processor communicates the I/O address via a set of wires normally included as part of the I/O bus. The command to the I/O function is transmitted over the data lines in the I/O bus.
The I/O addresses of I/O functions are typically written in the Basic Input/Output System (BIOS) that corresponds to the platform of the computer system, an operating system installed in the computer system, and device drivers written for the I/O functions. Computer systems using an I/O addressing scheme rely on the BIOS, the operating system, and device drivers to provide the processor with the correct I/O addresses to the I/O functions in the computer system. A problem occurs when a computer system is configured with a BIOS, operating system, or device driver that does not correspond to the platform of the computer system or when an I/O function is no longer at an I/O address that the BIOS, operating system, or device driver indicates. In these situations, an error would occur when the processor attempts to access an I/O function that does not exist at the I/O address indicated by the BIOS.
An apparatus according to an embodiment of the present invention is disclosed. The apparatus includes an input/output (I/0) address verification unit that determines whether an I/0 address received from a processor is protected. An interrupt generator is coupled to the I/O address verification unit. The interrupt generator generates an interrupt if the I/O address is protected. An interrupt recorder is coupled to the address verification unit. The interrupt recorder records a cause of the interrupt.